1. Field of the Invention
The invention relates to built in test circuitry having a clock duty cycle based access timer combined with standard stage clocked output register.
2. Background Art
When performing maximum frequency (f max) analysis on microprocessors, testers can simply increase the global clock frequency until the system fails. This does not give good insight into the maximum frequency or the maximum performance of the individual parts of the microprocessor or even the amount of guard band that is built into a microprocessor or integrated circuit. Increasing the frequency only tells you the f max of the slowest component.
By way of exemplification, one such critical component is the SRAM and another such critical component is a logic unit.
In addition to knowing the maximum sustainable frequency of the element, it is often important to know the true data access times of the elements on a chip.
Elaborate clock choppers have been used in the past, but these circuits can be quite large and take up valuable real estate. In the case of a SRAM, such large circuitry would need to be placed outside of the SRAM macro. Placing such critical timing circuits away from the element under test will result in inaccurate timing results. Thus, a need exists for a more compact solution to track timing delays in circuit elements.